Senior IP Design Verification Engineer (5-10 years experience)

About the role

As a Senior IP Design Verification Engineer you will ensure functional correctness and quality of advanced silicon IPs for next‑generation System‑on‑Chip platforms. You will own the pre‑silicon verification flow from planning through sign‑off, building robust UVM/SystemVerilog environments and debugging complex issues across IP and system boundaries.

Key responsibilities

• Plan, execute and sign‑off pre‑silicon verification of silicon IP, including UCIe interoperability.
• Develop, enhance and maintain verification environments, testbenches, test cases, checkers and coverage models.
• Run simulations and regressions, analyse failures, debug issues and drive root‑cause resolution with IP, integration and system teams.
• Track verification progress, report status, highlight risks early and propose mitigation actions.
• Review verification results for process compliance and contribute to technical reviews.
• Mentor junior engineers on verification methodology and debugging techniques.

Required profile

• 5‑10 years of experience in design verification of silicon IP.
• Strong understanding of pre‑silicon verification flow and sign‑off criteria.
• Experience working with advanced interfaces and protocols such as UCIe and AXI.
• Proven ability to collaborate with cross‑functional IP, integration and system teams.

Required skills

• UVM
• SystemVerilog
• UCIe
• AXI