ASIC Layout Design Engineer (Analog)

About the role

We are looking for an ASIC Layout Design Engineer with strong analog layout expertise to join our team in Hanoi for future MEMS sensor projects. The role focuses on delivering high‑quality ASIC layouts and supporting the tape‑out process.

Key responsibilities

• Design analog layouts from block level to top‑level IC integration.
• Perform physical verification for advanced ASICs used in MEMS sensor applications.
• Collaborate with international design teams to ensure timely and accurate layout delivery.
• Manage the complete tape‑out flow in coordination with the wafer foundry.
• Work with digital backend engineers to generate DEF files for place‑and‑route and integrate digital layout.
• Partner with CAD engineers to continuously improve PDKs and design environments.

Required profile

• Bachelor’s or Master’s degree in Microelectronics or Electrical Engineering with focus on analog/digital circuits and semiconductor physics.
• Proven experience in analog/mixed‑signal IC layout (e.g., ADCs, DACs, PLLs, LDOs, charge pumps, bandgap).
• Knowledge of TSMC 28nm‑152nm, SMIC 110nm, and TZ 180nm BCD SOI technologies and design rules.

Required skills

• Cadence Virtuoso for layout design.
• Verification tools such as Calibre, PVS, and Assura.