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Senior IP Design Verification Engineer

Bosch Group · Thành phố Hồ Chí Minh

Senior 🇬🇧 English
UVM OVM AXI VIP AXI protocol UCIe PCIe Gen3/4/5 USB3 DDR4 Ethernet CSI2 I3C gate-level simulation

Job description

About the role

We are looking for a Senior IP Design Verification Engineer to lead pre‑silicon verification of silicon IP blocks, including UCIe interoperability, within our Ho Chi Minh City development centre. You will work closely with IP, integration and system teams to ensure high‑quality verification deliverables.

Key responsibilities

  • Own and execute silicon‑IP pre‑silicon verification from planning through sign‑off.
  • Develop, enhance and maintain verification environments, testbenches, test cases, checkers and coverage models.
  • Run simulations and regressions, analyse failures, debug issues and drive root‑cause resolution.
  • Track verification progress, report status, highlight risks early and propose mitigation actions.
  • Review verification results, ensure process compliance and contribute to technical reviews.
  • Guide junior engineers on verification methodology and debugging approaches.

Required profile

  • 5+ years of experience in ASIC/SoC design verification.
  • Strong knowledge of the ASIC/SoC development lifecycle.
  • Hands‑on experience with OVM/UVM methodologies using SystemVerilog.
  • Experience in testbench development, test case creation, regression runs and coverage analysis.
  • Experience with AXI VIP and AXI protocol verification; UCIe experience is highly preferred.
  • Familiarity with PCIe Gen3/4/5, USB3, DDR4/5, Ethernet, CSI2, I3C and related standards.
  • Experience with gate‑level and timing‑constraint simulations.
  • Strong root‑cause analysis and debugging skills across testbench, integration and IP boundaries.
  • Fluent written and spoken English.

Required skills

  • SystemVerilog
  • UVM/OVM methodology
  • AXI VIP
  • AXI protocol
  • UCIe (preferred)
  • PCIe Gen3/4/5
  • USB3
  • DDR4/5
  • Ethernet
  • CSI2
  • I3C
  • Gate‑level simulation
  • Timing‑constraint simulation

What we offer

  • Competitive compensation package.
  • Opportunity to work on cutting‑edge silicon IP for automotive and industrial applications.
  • Collaborative environment with global engineering teams.

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Published 1 tháng trước

Expires 2 tuần tới

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Bosch Group

Thành phố Hồ Chí Minh